Direct memory access (DMA) controllers allow certain hardware subsystems within a computing system to access system memory somewhat independent of a central, microprocessor unit. To illustrate general DMA functionality, consider the example of FIG. 1, which illustrates a digital system 100 including a microprocessor 102, memory 104, DMA controller 106 and input/output block 108, all of which are operably coupled via a system bus 110. Without the DMA controller 106, when the microprocessor 102 is required to transfer large amounts of data in memory 104 or is required to write data to or read data from I/O block 108 or another system peripheral, the microprocessor 102 is typically fully occupied for the entire duration of read or write operations during the transfer. With the DMA controller 106, however, the microprocessor 102 programs the DMA controller 106 to handle the data transfer and, after programming the DMA controller 106, the microprocessor 102 can go about other tasks. After being programmed, the DMA controller 106 transfers the data in a somewhat autonomous fashion, and asserts an interrupt request (IRQ) to notify the microprocessor 102 that the data transfer is complete. In this way, the microprocessor 102 can off-load large data transfers to the DMA controller 106 and use its own resources for more suitable tasks. Hence, DMA controllers may be useful any time a microprocessor struggles to efficiently transfer data, where the microprocessor needs to perform useful work while waiting for a relatively slow I/O data transfer, or in other suitable instances.
While DMAs can improve the efficiency of data transfers for digital processing systems, DMAs also have the potential to wreak havoc on these systems if there are any bits in memory that have been corrupted and which the DMA acts upon.